The present technique relates to a semiconductor device, a manufacturing method of a semiconductor device, a protective element, and a manufacturing method of a protective element.
A compound semiconductor-based field effect transistor (FET) having a compound semiconductor layer such as a GaAs-based layer has high electron mobility and therefore the frequency characteristic thereof with an re-channel is favorable. Presently, examples of the FET using an n-channel used for a high-frequency band include HEMT and JPHEMT (refer to e.g. Japanese Patent Laid-open No. Hei 11-150264 (hereinafter, referred to as Patent Document 1)). The HEMT is the abbreviation of the high electron mobility transistor and the JPHEMT is the abbreviation of the junction pseudomorphic high electron mobility transistor.
A switching element such as a field effect transistor for large current is required to have a high reverse withstand voltage and low on-resistance. However, in the compound semiconductor-based field effect transistor (hereinafter, referred to as the FET), a surge resistance of its gate electrode and drain electrode is not so high as that required for the FET having desired use purpose, structure, and size.
There have been proposed structures in which a protective element configured to protect the gate electrode and the drain electrode from a surge is incorporated in a FET (refer to e.g. Japanese Patent Laid-open Nos. 2006-32582, 2002-343813, 2010-10262, and 2008-41784 (hereinafter, referred to as Patent Documents 2 to 5, respectively)).
For example, in a structure of Patent Document 2, a channel layer and a barrier layer are sequentially stacked over a GaAs semiconductor substrate with the intermediary of a buffer layer. An n+GaAs layer is formed on the barrier layer and an n−GaAs layer is formed on the n+GaAs layer. A p-type emitter region and a p-type collector region are formed on the surface of the n−GaAs layer.
In this structure, a PNP protective element is formed by a PN junction formed between the p-type emitter region and the n+GaAs layer and the n−GaAs layer and a PN junction formed between the p-type collector region and the n+GaAs layer and the n−GaAs layer.
In this PNP protective element, a current flows in only the n−GaAs layer in normal operation and a current flows in not only the n−GaAs layer but also the n+GaAs layer when a surge enters the device. Thus, the compound semiconductor device including this PNP protective element has enhanced surge resistance.
For example, in a semiconductor device described in Patent Document 5, a buffer layer of a GaAs film, a first carrier supplying layer of an n+AlGaAs film, a first spacer layer of an i-AlGaAs film, a channel layer of an InGaAs film, a second spacer layer of an i-AlGaAs film, a second carrier supplying layer of an n+AlGaAs film, a barrier layer of an n−AlGaAs film, and a first conductive layer of an n+GaAs film are sequentially formed over a GaAs semiconductor substrate by an epitaxial growth method. Furthermore, a first interlayer insulating film of e.g. a silicon nitride film or a silicon oxide film is formed thereon.
In this semiconductor device, two apertures for diffusion are formed in the first interlayer insulating film by etching with use of a resist mask and a P-type atom such as zinc (Zn) is diffused from the apertures for diffusion into the first conductive layer to form a second conductive layer. Thereby, a PN junction surface is formed between the first conductive layer and the second conductive layer. By connecting the second conductive layer formed in this manner by a first metal film, a connection of first conductive layer (N-type)-second conductive layer (P-type)-first metal film-second conductive layer (P-type)-first conductive layer (N-type) is made, so that a protective element having an NPN structure is formed.